Chemical Mechanical Polishing (CMP) is a part of the chip fabrication process that requires a uniform distribution of metal and silicon over the surface of the chip. To achieve this distribution, pieces of interconnect (metal or silicon) must be inserted into available spaces in low-density regions of the chip. This interconnect insertion is called dummy metal filling or simply dummy filling, and the inserted interconnect is called dummy metal.
Most fabrication processes require a minimum density for the interconnects on each layer of a multi-layer chip design. The interconnect density for a region is the sum total of the area of all interconnect in that region divided by the area of the region. Fabrication processes typically partition each layer of the design into rectangular regions, called tiles, and specify that the interconnect density of each tile meet a minimum density requirement.
The process of determining the number and placement of dummy metal is typically preformed by a dummy fill software tool after routing and timing closure during chip design flow. The dummy fill tool examines the tiles in each layer of the design and determines whether each tile has an interconnect density equal to or greater than the specified minimum density. If the interconnect density does not meet the minimum density, then the dummy fill tool inserts dummy metal in free regions of the tile.
Because dummy filling is one of the last steps in the chip design flow, it is important that the dummy metal is inserted into the chip in such a manner that minimizes any negative impact to timing. That is, patterning the dummy metal too close to signal nets increases capacitance between the dummy lines and the signal wires. The increased capacitance can affect the signal nets by slowing the transmission speed of signals, thereby degrading overall performance of the integrated circuit.
Therefore, a common goal of dummy filling techniques is the minimization of the parasitic capacitance introduced by the dummy metal. The parasitic capacitance introduced by a piece of dummy metal on a signal wire is inversely proportional to the distance between the two. This means that to minimize timing impact, dummy metal must be placed far away from signal nets.
Of signal nets, clock nets are of particular importance. Care must be taken to minimize the negative timing impact to clock nets. Traditionally, this has been achieved with a simplistic approach. The dummy fill tool is programmed to maintain a larger distance between wires of clock nets and the inserted dummy metal. This large dummy to clock distance is arrived at by studying the effect on timing that the inserted dummy metal has at various distances from clock nets in sample designs, and then hardcoding the distances into the dummy fill libraries for each type of process technology.
However, hardcoding a large “stay-away” distance between dummy metal and clock nets may lead to less available space in each tile for dummy metal insertion. New process technologies increasingly demand higher minimum density values and more timing-aggresive designs. In this scenario, use of the simple large dummy-to-clock distance methodology is disadvantageous. This is because it is often impossible to insert enough dummy metal into a tile to meet the required minimum density without reducing the large dummy-to-clock distance. In this case, traditional metal-fill tools complete their run without reaching minimum density in some tiles, requiring a second run of the tool for the problematic tiles in which the dummy-to-clock distance is reduced. If there is more than one such tile requiring a rerun, and the dummy fill tool can handle only one tile at a time, multiple runs may be needed: one for each tile. Such an involved, iterative process can significantly impact the design schedule.
Accordingly what is needed is an algorithm for dummy fill that minimizes the negative timing impact of dummy metal on clock nets, while at the same time achieving minimum density in a single run. The present invention addresses such a need.